Object Orientated Spice Parser/AST browser (Developer)
We built an object orientated Spectre Spice netlist parser and AST browser as a
front-end integration to an analog synthesis EDA tool. This included a constraint
management engine, allowing for different netlisting modes.
Power/Heat Analysis with Calibre/Eldo/Spectre Integration (Developer)
We built a generic spice power simulation methodology around the
Eldo/Spectre spice environments and integrated these with Calibre LVS
circuit extraction and a 3rd party temperature analysis tool. This
involved running/parsing Spice power simulations, writing Calibre LVS
rules, parsing (using Perl) spice input schematics/simulation -results and
incorporating the composite data into a temperature convergent simulation.
3rd Party Analog Design Environment Integration (Developer)
We integrated a 3rd party analog synthesis tool into the Cadence Virtuoso/Composer tools
environment. This involved developing an intuitive UI, writing schematics and managing analog
constraints across the 2 toolsets. The interface was developed in Skill and wrote TCL directives
for the 3rd party tool.
Schematic Re-Referencer Tool (click here for presentation)
A Cadence Composer schematic re-referencer was
created to facilitate schematic process porting in
a mixed signal/analog design IP provider. This included CDF mapping,
library migration and the intelligent processing of circuit
parameters to facilitate porting.
Mixed Signal Floorplanner (Lead Architect)
We acted as architects to the mixed signal floorplanning services
offering from Cadence. In this role we worked on the preliminary
spec and with Cadence developers during the implementation to
ensure consistency. This methodology allows a mixed signal designer
to go from a schematic to an accurately sized floorplan prior to
block layout availability.
Process Design Kit Development Platform (Lead Architect)
This was a methodology at
Cadence for automating the creation of Process Design
Kits (PDK's). This includes an intelligent XML based design
envionment optimization tool, and various programs to synthesize
pcells in the target process, generate verification rules decks,
techFiles, compile CDF templates, fixed layout IP etc. The
intended audience was Cadence internal developers and
onsite at customer locations by Cadence consulting teams.
Virtuoso Custom Designer (Lead Architect)
This is the official Cadence methodology for Mixed Signal IC
layout using pCell generator software, Virtuoso XL, Virtuoso
Custom Placer, Virtuoso Custom Router and Diva/Assura verification
environments. As architects of the flow we directed a cross-functional
Cadence team from the Process Design Factory, Methodology Services,
Marketing and RD during the creation of this environment.
In addition to defining the methodology we also coded various
mixed-signal style floorplanning utilities as part of the VCD
VXL environment.
Genesis Unified Design Constraints Environment
We were instrumental in the development of a common constraints
environment across the Cadence toolset and specification of the Genesis
constraints database schema. This involved liasing across Cadence R&D
to define a common design constraints understanding and the design of a
UML C++ object orientated database schema that will be used as the repositary
for these constraints in the next generation Cadence tools offering.
Design Constraints Manager Import/Export Methodology
We developed an ascii DCDL (Design Constraints Description Language)
parser/writer and gui to the Cadence Constraint Manager database utilizing the
CMB database API. This tool will be part of the forthcoming Cadence Sierra
(4.4.7) release of VXL.
Hercules integration for Cadence 446 Virtuoso Layout Editor
A Skill interface was written to fully encapsulate the Avanti Hercules LVS/DRC
methodologies providing a seamless physical verification environment from the
Cadence Virtuoso toolset.
Synthesis to Back Annotated Layout
A batch netlist/floorplanning/place-and-route methodology was developed at
a high performance microprocessor startup.
This integrated the following tools:
- Design Planner (Cadence Design)
- Silicon Ensemble (Cadence Design)
- Caliber/xCaliber (Mentor Graphics)
The resulting environment allowed RTL designers to get placed and routed,
back-annotated parasitic information into static timing analysis in a fully encapsulated batch driven flow.
Unified Verification and Parasitic Extraction Tool
A Perl based parasitic extraction environment was developed that encapsulated the following tools:
- Calibre (Mentor Graphics)
- xCalibre RC (Mentor Graphics)
- Columbus RC (Sequence Design)
- Quick Cap Field Solver (Random Logic)
- Raphael Field Solver (Avanti)
This tool enabled users to run verification and extraction using multiple
vendor tools from one unified perl based interface. In the extraction
methodology a set of nets could be characterized and based on that nets
characteristics (% coupling, length, max lumped C etc) the appropriate
extraction tool was selected. The process of selecting the appropriate
extraction tool was transparent to the user.
Clock-Tree Extraction/Analysis Tool
A clock tree analysis program was developed in the Cadence/Mentor environment.
This took as input Cadence schematics and layout and returned a spice netlist for verification.
Layout Process Migration System
An abstract set of Cadence Pcell library generators were written and a
methodology for placing these down in a technology independent fashion was
developed. This involved the use of placement macros such as "As Close As Possible"
and "Align Edges". A CCT device level router batch mode interface was written
to allow automatic routing and in the case of manually created layout a suite
of smart migration programs to recognize and map minimum size geometric patterns
was developed. Finally a Sagantec Dream interface was written to provide process
porting via design rule compaction.
Cache/Register-File Compiler (datapath tiler)
Technology independent layout generators were developed for the tag/cache
sense-amp/column-decode/buffer layout blocks. These were integrated with a datapath
tiling engine to facilitate process porting. This was developed using Cadence Skill/Perl
