Novel Design Techniques for the Design of an Embedded Microprocessor Core

Simon Butler.

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SandCraft Inc. develops 64-bit microprocessor cores for embedded applications based on the MIPS architecture. The company is operating at the leading edge of the semiconductor industry since its customers are creating the most powerful systems. SandCraft's designs will power consumer products requiring the latest processor technology, such as home entertainment systems, web browsers, networking products, digital TV set-top boxes and laser printers.

SandCraft developed a custom flow that combines the best tools of the industry. The design is dominated by custom implementation (approximately 80% of the overall chip) complemented with standard cells. Cadence's Design Planner III and Silicon Ensemble are used for the chip planning and place-and-route respectively. Mentor Graphics' Calibre is used for DRC and LVS.

The design flow implemented by SandCraft was driven the business objectives of the company as well as by the desire to produce the best technology. SandCraft differentiates its product based on superior price/performance. The lower price objective means that smaller die size was a key development objective. The other part of the price consideration was maintaining low power consumption for the chip: this resulted in the use of plastic packages.

The performance requirements drove the custom layout approach for 80% of the design. The tools used in that environment were the Cadence Composer schematic editor and the Virtuoso layout editor. The circuit designers were the key drivers in this methodology. The chip performance was taken into account during the early stages of the schematics implementation. Also, key architecture features of the design required the approval of the circuit designers before they were incorporated in the chip. The circuit designers would review the recommendations of the architecture team from the performance perspective. The circuit designers also handled the physical design to maintain the focus on performance throughout the design flow.

An automated flow was implemented for the other 20% of the design. The complete flow from RTL through place-and-route, extraction and backannotation into synthesis - including ECOs - was encapsulated in a "push button" batch environment.

SandCraft placed special emphasis on the interconnect extraction portion of their design flow because the engineers recognize the importance of this step to achieve optimal chip performance. With the very deep sub-micron process technology targeted by SandCraft, it is an accepted fact that the interconnect dominates the performance of the overall chip. The interconnect dominates the transistor in their respective contribution to the overall chip delay for chips designed with 0.25um technology and below.

An extraction flow was developed at SandCraft based on three issues:

• accuracy
• data explosion
• run times

An interface was developed that enabled the engineers to drive interconnect extraction of critical nets based on three different tools. The interface transparently assigns the net extraction to the appropriate tool based on a threshold of the measured lumped capacitance.

Mentor Graphics' xCalibre is used for a simple lumped capacitor extraction. A threshold measurement is applied to the results of this initial net extraction. When additional accuracy is required, two choices are available. The intermediate level is to complete the extraction based on the distributed RC mode of xCalibre. When the best accuracy is necessary, Frequency Technology's Columbus parasitic extractor is invoked which produces distributed RC models. The results of the three extraction approaches are all combined in the parasitic database (PDB) of xCalibre. A Spice netlist is then written out that combines the output of the three extractors. This approach results in very good accuracy while limiting the run times and the size of the data generated by focusing the high accuracy extraction on the most critical nets only.

The accuracy of the different extractors used was calibrated before this strategy was implemented. The calibration was based on the QuickCap field solver. Columbus has consistently demonstrated extraction accuracy within 2% of the field solver with 5% maximum error. xCalibre results were within 10% of the field solver.

A set of critical net capacitances measured using QuickCap is consistently kept available for all designers through a web page. The engineers can consult these data points for reference. For each extraction job, a program will automatically run QuickCap on some chosen critical nets. The nets are selected to cover all known corner cases. The results of the QuickCap field solver extraction - the "gold standard" can then be compared to the other extraction tools. If the results are not satisfactory, warning messages will automatically be e-mailed to the designers.

This thresholding technique for the extraction has been very successful. SandCraft is investigating further refinements of this approach in which a more comprehensive criteria than a simple lumped C analysis would be applied to delineate the threshold. Possible enhancements are to tie in static timing analysis results and signal integrity data.

This innovative methodology has been tested on a recently completed design and will be used for the development of SandCraft's next generation processor. This new core is targeted for a 0.18um process and will run at speeds of 350MHz and above.

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